View TPS71319-16_9045259.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features description applications tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 dual 250 ma output, ultralow noise, high psrr, low-dropout linear regulator with integrated svs dual 250 ma high-performance rf ldos the tps713xx family of low-dropout (ldo) voltage regulators is tailored to noise-sensitive and rf appli- integrated supply voltage supervisor cations. these products feature dual 250 ma ldos monitors v out2 with ultralow noise, high power-supply rejection ratio available in fixed and adjustable (psrr), and fast transient and start-up response. voltage options (1.2 v to 5.5 v) these devices also feature an integrated supply high psrr: 65 db at 10 khz voltage supervisor (svs) that monitors the voltage at out2 and will assert if the voltage falls to 95% ultralow noise: 32 vrms (typical) of the measured output. each regulator fast start-up time: 60 s output is stable with low-cost 2.2 f ceramic output stable with 2.2 f ceramic capacitor capacitors and features very low dropout voltages (125 mv typical at 250 ma). each regulator achieves excellent load/line transient response fast start-up times (approximately 60 s with a very low dropout voltage: 125 mv at 250 ma 0.001 f bypass capacitor) while consuming very low independent enable pins quiescent current (300 a typical with both outputs enabled). when the device is placed in standby thermal shutdown and independent current mode, the supply current is reduced to less than limit 0.3 a typical. each regulator exhibits approximately available in thermally-enhanced son 32 vrms of output voltage noise with v out = 2.8 v package: 3mm x 3mm x 1mm and a 0.01 f noise reduction (nr) capacitor. appli- cations with analog components that are noise-sensitive, such as portable rf electronics, will cellular and cordless phones benefit from high psrr, low noise, and fast line and load transient features. the tps713xx family is wireless pda/handheld products offered in a thin 3mm x 3mm son package and is pcmcia/wireless lan applications fully specified from -40 c to +125 c (t j ). digital camera/camcorder/internet audio dsp/fpga/asic/controllers and processors please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2004?2005, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
www .ti.com e n 1 n c e n 2 f b 2 / n c n r 1 0 98 7 6 i n r e s e t o u t 1 o u t 2 g n d 12 3 4 5 d r c p a c k a g e 3 m m x 3 m m s o n ( t o p v i e w ) 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 00 p s r r ( d b ) 1 0 1 0 0 1 k 1 0 k 1 0 0 k 1 m 1 0 m f r e q u e n c y ( h z ) p s r r ( r i p p l e r e j e c t i o n ) v s f r e q u e n c y v o u t = 2 . 8 v ( a d j ) c o u t = 2 . 2 m f c n r = 0 . 0 1 m f i o u t = 1 m a i o u t = 2 5 0 m a
absolute maximum ratings power dissipation ratings tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) voltage (t j ) package- specified lead temperature package ordering transport product v out1 v out2 (designator) range (t j ) marking number media, quantity tps71319drct tape and reel, 250 tps71319 1.8 v adjustable son-10 (drc) -40 c to +125 c arp tps71319drcr tape and reel, 3000 tps71334drct tape and reel, 250 tps71334 3.3 v adjustable son-10 (drc) -40 c to +125 c aro tps71334drcr tape and reel, 3000 (1) for the most current package and ordering information, see the package ordering addendum located at the end of this data sheet. over operating junction temperature range unless otherwise noted (1) tps713xx unit v in range -0.3 to 6.0 v v reset range -0.3 to v in + 0.3 v v en1 , v en2 range -0.3 to v in + 0.3 v v out range -0.3 to 6.0 v peak output current internally limited output short-circuit duration indefinite continuous total power dissipation see dissipation ratings table junction temperature range, t j -40 to +150 c storage temperature range -65 to +150 c esd rating, hbm 2 kv esd rating, cdm 500 v (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the electrical characteristics is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. derating factor t a 25 c t a = 70 c t a = 85 c board package r q jc r q ja above t a = 25 c power rating power rating power rating high-k (1) drc 48 52 19 mw/ c 1.92 w 1.06 w 0.77 w (1) the jedec high-k (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on the top and bottom of the board. 2 www .ti.com
electrical characteristics tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 over operating temperature range (t j = -40 c to +125 c), v in = highest v out(nom) + 1.0 v or 2.7 v (whichever is greater), i out = 1 ma, v en1, 2 = 1.2 v, c out = 10 f, c nr = 0.01 f, and adjustable ldos are tested at v out = 3.0 v, unless otherwise noted. typical values are at t j = 25 c. parameter test conditions min typ max unit v in input voltage range (1) 2.7 5.5 v v fb internal reference (adjustable ldos) 1.200 1.225 1.250 v output voltage range v fb 5.5 - v do v (adjustable ldos) v out nominal t j = 25 c, i out = 0 ma -1.5 +1.5 accuracy (1) % over v in , v out + 1.0 v v in 5.5 v, -3 1 +3 i out , and t 0 a i out 250 ma d v out %/ d v in line regulation (1) v out + 1.0 v v in 5.5 v 0.05 %/v d v out %/ d i out load regulation 0 a i out 250 ma 0.8 %/ma 2.8 v, dropout voltage (2) v do 2.85 v i out1 = i out2 = 250 ma 125 230 mv (v in = v out(nom) - 0.1v) adjustable i cl output current limit v out = 0.9 v out(nom) 400 600 800 ma one ldo i out = 1 ma (enabled channel) 190 250 enabled i gnd ground pin current a both ldos i out1 = i out2 = 1 ma to 250 ma 300 600 enabled v en 0.4 v, 0 v v in 5.5 v, i shdn shutdown current (3) 0.3 2.0 a reset open i fb fb pin current (adjustable ldos) 0.1 1 a no c nr , i out = 250 ma 80.0 v out output noise voltage, v n vrms bw = 10 hz - 100 khz c nr = 0.01 f, i out = 250 ma 11.8 v out f = 100 hz, i out = 250 ma 65 power-supply rejection ratio psrr db (ripple rejection) f = 10 khz, i out = 250 ma 65 t str startup time v out = 2.85 v, r l = 30 w , c nr = 0.001 f 60 s v ih enable threshold high (en1, en2) 1.2 v in v v il enable threshold low (en1, en2) 0 0.4 v i en enable pin current (en1, en2) v in = v en = 5.5 v -1 1 a minimum v in for valid reset i reset = 10 a 0.6 v v reset, lo reset output low voltage i reset = 1 ma 0.4 v i lkg, reset reset leakage current v in = v reset = 5.5 v 10 500 na v it reset threshold voltage v out2 falling (4) 92.5 97.5 %v out v hys reset threshold hysteresis v out2 rising (4) 0.5 %v out t d reset delay time 50 100 200 ms t p reset propagation delay 10 s shutdown temp increasing +160 t sd thermal shutdown temperature c reset temp decreasing +140 under-voltage lockout threshold v in rising 2.25 2.65 v uvlo under-voltage lockout hysteresis v in falling 100 mv (1) minimum v in = v out + v do or 2.7 v, whichever is greater. (2) v do is not measured for 1.8 v regulators since minimum v in = 2.7 v. (3) for the adjustable version, this applies only after v in is applied; then v en transitions from high to low. (4) reset threshold and hysteresis is a percentage of the measured output. 3 www .ti.com
tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 functional block diagram table 1. terminal functions terminal description name drc in 1 unregulated input supply. a 0.1 f capacitor should be connected from in to gnd. gnd 5, pad ground output of the regulator. a small 2.2 f ceramic capacitor is required from this pin to ground to assure out1 3 stability. out2 4 same as out1 but for ldo2. driving the enable pin (en) high turns on ldo1. driving this pin low puts ldo1 into shutdown mode, en1 10 reducing operating current. the enable pin should be connected to in if not used. en2 8 same as en1 but controls ldo2. nc 9 no connection. fb2/nc 7 feedback for ch2 adjustable version; no connection for non-adjustable ch2. nr 6 noise reduction pin; connect an external bypass capacitor to reduce ldo output noise. open-drain reset output; monitors out2. a 10 k w to 1 m w pull-up resistor is suitable for most reset 2 applications. the open-drain reset pull-up voltage should not exceed v dd + 0.3 v. 4 www .ti.com c u r r e n t l i m i t t h e r m a l s h u t d o w n v r e f 1 . 2 2 5 v u v l o 3 0 m a 9 0 k w e n 1 o u t 1 i n c u r r e n t l i m i t o u t 2 n r e n 2 2 5 0 k w q u i c k s t a r t 5 p f t p s 7 1 3 x x f i x e d / f i x e d f b 2 r e s e t 0 . 9 5 v r e f 1 0 0 m s d e l a y ( v f b 2 r i s i n g )
typical characteristics tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 for all voltage versions at t j = 25 c, v in = v out(nom) + 1 v, i out = 1 ma,v en = 1.2 v, c out = 2.2 f, and c nr = 0.01 f, unless otherwise noted. output voltage vs input voltage output voltage vs output current figure 1. figure 2. dropout voltage vs input voltage output voltage vs temperature (adjustable outputs) figure 3. figure 4. dropout voltage vs output current dropout voltage vs junction temperature figure 5. figure 6. 5 1 . 0 0 . 50 - 0 . 5 - 1 . 0 - 1 . 5 v o u t ( % ) j u n c t i o n t e m p e r a t u r e ( c ) - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 i o u t = 1 0 m a i o u t = 2 5 0 m a i o u t = 1 2 5 m a 2 0 0 1 8 0 1 6 0 1 4 0 1 2 0 1 0 0 8 0 6 0 4 0 2 00 d r o p o u t v o l t a g e ( m v ) 2 . 7 3 . 1 3 . 3 3 . 5 3 . 9 4 . 1 4 . 3 4 . 5 4 . 7 4 . 9 v i n ( v ) t j = - 4 0 c t j = + 2 5 c t j = + 1 2 5 c 3 . 7 2 . 9 2 0 0 1 5 0 1 0 0 5 00 d r o p o u t v o l t a g e ( m v ) 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 i o u t ( m a ) t j = + 2 5 c t j = - 4 0 c t j = + 1 2 5 c a d j u s t a b l e s e t t o 2 . 8 v www .ti.com 2 5 0 2 0 0 1 5 0 1 0 0 5 00 d r o p o u t v o l t a g e ( m v ) - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 j u n c t i o n t e m p e r a t u r e ( m a ) i o u t = 2 5 0 m a a d j u s t a b l e s e t t o 2 . 8 v 1 . 0 0 . 8 0 . 6 0 . 4 0 . 20 - 0 . 2 - 0 . 4 - 0 . 6 - 0 . 8 - 1 . 0 v o u t ( % ) 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 6 . 0 v i n ( v ) + 2 5 c + 1 2 5 c - 4 0 c 1 . 0 0 . 8 0 . 6 0 . 4 0 . 20 - 0 . 2 - 0 . 4 - 0 . 6 - 0 . 8 - 1 . 0 v o u t ( % ) 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 i o u t ( m a ) + 2 5 c - 4 0 c + 1 2 5 c
tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 typical characteristics (continued) for all voltage versions at t j = 25 c, v in = v out(nom) + 1 v, i out = 1 ma,v en = 1.2 v, c out = 2.2 f, and c nr = 0.01 f, unless otherwise noted. ground current vs input voltage ground pin current vs i out figure 7. figure 8. ground pin current vs junction temperature ground pin current vs junction temperature (disabled) figure 9. figure 10. tps71334 current limit vs junction temperature line transient response figure 11. figure 12. 6 5 0 0 4 5 0 4 0 0 3 5 0 3 0 0 2 5 0 2 0 0 1 5 0 1 0 0 5 00 i g n d ( n a ) j u n c t i o n t e m p e r a t u r e ( c ) v e n 1 = v e n 2 = 0 . 4 v v i n = 3 . 8 v - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 v o u t 1 v o u t 2 v i n 4 . 3 v 3 . 8 v 1 0 m v / d i v 1 0 m v / d i v 1 0 0 m s / d i v i o u t = 2 5 0 m a i o u t = 1 m a c o u t 1 = c o u t 2 = 1 0 m f v o u t 2 s e t t o 1 . 2 2 5 v 8 0 0 7 5 0 7 0 0 6 5 0 6 0 0 5 5 0 5 0 0 4 5 0 4 0 0 c u r r e n t l i m i t ( m a ) j u n c t i o n t e m p e r a t u r e ( c ) - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 www .ti.com 4 0 0 3 7 5 3 5 0 3 2 5 3 0 0 2 7 5 2 5 0 2 2 5 2 0 0 i g n d ( m a ) 2 . 7 3 . 2 3 . 7 4 . 2 4 . 7 5 . 2 5 . 7 v i n ( v ) + 2 5 c - 4 0 c + 1 2 5 c 4 0 0 3 7 5 3 5 0 3 2 5 3 0 0 2 7 5 2 5 0 2 2 5 2 0 0 i g n d ( m a ) 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 i o u t ( m a ) + 2 5 c - 4 0 c + 1 2 5 c 4 0 0 3 7 5 3 5 0 3 2 5 3 0 0 2 7 5 2 5 0 2 2 5 2 0 0 i g n d ( m a ) j u n c t i o n t e m p e r a t u r e ( c ) v e n 1 = v e n 2 = 1 . 2 v v i n = 3 . 8 v - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5
tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 typical characteristics (continued) for all voltage versions at t j = 25 c, v in = v out(nom) + 1 v, i out = 1 ma,v en = 1.2 v, c out = 2.2 f, and c nr = 0.01 f, unless otherwise noted. tps71334 load transient response tps71334 and v out2 crosstalk channel-to-channel isolation vs frequency figure 13. figure 14. tps71334 turn-on/off response tps71334 and v out2 crosstalk power-up/power-down figure 15. figure 16. noise spectral density total noise vs c nr c out = 2.2 f figure 17. figure 18. 7 v o u t 2 v o u t 1 i o u t 1 2 m v / d i v 1 0 0 m v / d i v 2 0 0 m a / d i v 2 0 m s / d i v 2 5 0 m a 1 0 m a c o u t 2 = 1 0 m f c o u t 1 = 1 0 m f v o u t 2 s e t t o 2 . 2 2 5 v 6 0 5 0 4 0 3 0 2 0 1 00 c h a n n e l i s o l a t i o n ( d b ) 0 . 1 1 1 0 1 0 0 1 k f r e q u e n c y ( h z ) c o u t 1 = c o u t 2 = 1 0 m f i o u t 1 = 0 m a t o 5 0 0 m a s i n u s o i d a l l o a d i o u t 2 = 2 5 m a a d j u s t a b l e s e t t o 3 . 3 v 2 0 m v / d i v 1 v / d i v v o u t 2 v o u t 1 v e n 1 5 0 m s / d i v c n r = 0 . 0 0 1 m f i o u t 1 = i o u t 2 = 2 5 0 m a c o u t 1 = c o u t 2 = 1 0 m f v o u t 2 s e t t o 1 . 2 2 5 v www .ti.com 1 v / d i v 5 0 m s / d i v i o u t 1 = i o u t 2 = 2 5 0 m a v o u t 2 v o u t 2 v i n v r e s e t 2 5 0 2 0 0 1 5 0 1 0 0 5 00 t o t a l n o i s e ( m v r m s ) 1 1 0 1 0 0 1 k 1 0 k 1 0 0 k c n r ( p f ) c o u t = 2 . 2 m f i o u t = 2 5 0 m a c o u t = 1 0 m f i o u t = 2 5 0 m a c o u t = 2 . 2 m f i o u t = 0 m a c o u t = 1 0 m f i o u t = 0 m a v o u t = 2 . 8 v ( a d j ) 3 5 0 3 0 0 2 5 0 2 0 0 1 5 0 1 0 0 5 00 1 0 0 1 k 1 0 k 1 0 0 k f r e q u e n c y ( h z ) s p e c t r a l n o i s e d e n s i t y ( n v / h z ) i o u t = 2 5 0 m a c n r = 0 . 1 m f v o u t = 2 . 8 v ( a d j ) i o u t = 1 m a
tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 typical characteristics (continued) for all voltage versions at t j = 25 c, v in = v out(nom) + 1 v, i out = 1 ma,v en = 1.2 v, c out = 2.2 f, and c nr = 0.01 f, unless otherwise noted. noise spectral density c out = 10 f noise spectral density vs c nr figure 19. figure 20. psrr (ripple rejection) vs frequency psrr (ripple rejection) vs frequency figure 21. figure 22. psrr (ripple rejection) vs v in - v out figure 23. 8 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 00 p s r r ( d b ) 1 0 1 0 0 1 k 1 0 k 1 0 0 k 1 m 1 0 m f r e q u e n c y ( h z ) v o u t = 2 . 8 v ( a d j ) c o u t = 2 . 2 m f c n r = 0 . 0 1 m f i o u t = 1 m a i o u t = 2 5 0 m a 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 00 p s r r ( d b ) 1 0 1 0 0 1 k 1 0 k 1 0 0 k 1 m 1 0 m f r e q u e n c y ( h z ) v o u t = 2 . 8 v ( a d j ) c o u t = 1 0 m f c n r = 0 . 0 1 m f i o u t = 1 m a i o u t = 2 5 0 m a 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 00 p s r r ( d b ) 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 v i n - v o u t ( v ) f = 1 k h z f = 1 0 k h z f = 1 0 0 k h z v o u t = 2 . 8 v ( a d j ) i o u t = 2 5 0 m a c o u t = 1 0 m f c n r = 0 . 0 1 m f www .ti.com 3 5 0 3 0 0 2 5 0 2 0 0 1 5 0 1 0 0 5 00 1 0 0 1 k 1 0 k 1 0 0 k f r e q u e n c y ( h z ) s p e c t r a l n o i s e d e n s i t y ( n v / h z ) i o u t = 2 5 0 m a c n r = 0 . 0 1 m f v o u t = 2 . 8 v ( a d j ) i o u t = 1 m a 1 8 0 1 6 0 1 4 0 1 2 0 1 0 0 8 0 6 0 4 0 2 00 1 0 0 1 k 1 0 k 1 0 0 k f r e q u e n c y ( h z ) s p e c t r a l n o i s e d e n s i t y ( n v / h z ) 0 . 0 0 1 m f 0 . 0 4 7 m f 0 . 0 1 m f 0 . 1 m f c o u t = 1 0 m f i o u t = 2 5 0 m a v o u t = 2 . 8 v ( a d j )
application information output noise input and output capacitor startup characteristics tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 1.8 v or less is chosen, the minimum recommended the tps713xx family of dual low-dropout (ldo) output capacitor is 4.7 f. any ceramic capacitor that regulators has been optimized for use in meets the minimum output capacitor requirements is noise-sensitive battery-operated equipment. the de- suitable. capacitors with higher esr may be used, vice features extremely low dropout, high psrr, provided the worst-case esr is less than 1 w . ultralow output noise, and low quiescent current (190 a typically per channel). when both outputs are disabled, the supply currents are reduced to less than 2a. a typical application circuit with sequencing the internal voltage reference is a key source of is shown in figure 24 . noise in an ldo regulator. the tps713xx has an nr pin that is connected to the voltage reference through a 250 k w internal resistor. the 250 k w internal resistor, in conjunction with an external ceramic bypass capacitor connected to the nr pin, creates a low-pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. to achieve a fast startup, the 250 k w internal resistor is shorted for 400 s after the device is enabled. because the primary noise source is the internal voltage reference, the output noise will be greater for higher output voltage versions. for the case where no noise reduction capacitor is used, the typical noise (vrms) over 10 hz to 100 khz is 30 times the output voltage. if a 0.01 f capacitor is used from the nr pin to ground, the noise (vrms) drops to 11.8 times figure 24. typical application circuit the output voltage. for example, the tps71334 with (with output sequencing) the adjustable output set to 2.8 v exhibits only 33 vrms of output voltage noise using a 0.01 f ceramic bypass capacitor and a 2.2 f ceramic output capacitor. requirements a 0.1 f or larger ceramic input bypass capacitor, connected between in and gnd and located close to to minimize startup overshoot, the tps713xx will the tps713xx, is required for stability. it improves initially target an output voltage that is approximately transient response, noise rejection, and ripple rejec- 80% of the final value. to avoid a delayed startup tion. a higher-value input capacitor may be necessary time, noise reduction capacitors of 0.01 f or less if large, fast-rise-time load transients are anticipated are recommended. larger noise reduction capacitors and the device is located several inches from the will cause the output to hold at 80% until the voltage power source. on the noise reduction capacitor exceeds 80% of the the tps713xx requires an output capacitor connec- bandgap voltage. the typical startup time with a ted between the outputs and gnd to stabilize the 0.001 f noise reduction capacitor is 60 s. once internal control loops. the minimum recommended one of the output voltages is present, the startup time output capacitor is 2.2 f. if an output voltage of of the other output will not be affected by the noise reduction capacitor. 9 t p s 7 1 3 3 4 g n d n r f b 2 i n o u t 1 e n 1 o u t 2 e n 2 r e s e t v i n v o u t 1 v o u t 2 0 . 1 m f 2 . 2 m f 2 . 2 m f c 1 1 0 0 k w 0 . 0 1 m f r 1 r 2 6 4 . 9 k w www .ti.com
programming the tps71202 (3) (1) dropout voltage (2) tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 adjustable ldo regulator the output voltage of the tps71202 dual adjustable the suggested value of this capacitor for several regulator is programmed using an external resistor resistor ratios is shown in figure 25 . if this capacitor divider, as shown in figure 24 . the output voltage is is not used (such as in a unity-gain configuration) or if calculated using equation 1 : an output voltage 1.8 v is chosen, then the minimum recommended output capacitor is 4.7 f instead of 2.2 f. where v ref = 1.225 v (the internal reference volt- age). the tps713xx uses a pmos pass transistor to resistors r2 and r4 should be chosen for approxi- achieve extremely low dropout. when (v in - v out ) is mately a 40 a divider current. lower value resistors less than the dropout voltage (v do ), the pmos pass can be used for improved noise performance, but will device is in its linear region of operation and the consume more power. higher values should be input-to-output resistance is the r ds, on of the pmos avoided because leakage current at fb increases the pass element. dropout voltages at lower currents can output voltage error. the recommended design pro- be approximated by calculating the effective r ds, on cedure is to choose r2 = 30.1 k w to set the divider of the pass element and multiplying that resistance by current at 40 a, and then calculate r1 using the load current. r ds, on of the pass element can be equation 2 : obtained by dividing the dropout voltage by the rated output current. for the tps71334, the r ds, on of the pass element is 84 m w . the dropout voltage of the tps713xx will be less for higher output voltage versions. this is because the pmos pass element to improve the stability and noise performance of the will have lower on-resistance due to increased gate adjustable version, a small compensation capacitor drive. can be placed between out and fb. for voltages 1.8 v, the value of this capacitor should be 100 pf. for voltages > 1.8 v, the approxi- mate value of this capacitor can be calculated as equation 3 : figure 25. tps71334 adjustable ldo regulator programming 10 c 1 ( 3 1 0 5 ) ( r 1 r 2 ) ( r 1 r 2 ) ( p f ) v o u t v r e f 1 r 1 r 2 www .ti.com r 1 v o u t v r e f 1 r 2 v o u t 2 1.225 v 1.5 v2.5 v 3.0 v 3.3 v 4.75 v r1 short 7.15 k w 31.6 k w 43.2 k w 49.9 k w 86.6 k w r2 open 30.1 k w 30.1 k w 30.1 k w 30.1 k w 30.1 k w output v oltage programming guide c1 open 100 pf 22 pf15 pf 15 pf 15 pf t p s 7 1 3 3 4 g n d n r f b 2 i n o u t 1 e n 1 o u t 2 e n 2 r e s e t v i n v o u t 1 v o u t 2 0 . 1 m f 2 . 2 m f 2 . 2 m f c 1 0 . 0 1 m f r 1 r 2
tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 output will remain unasserted during transients shorter than the reset circuit propagation delay (t p ). supervisor description even with a 2.2 f output capacitor, typical load the tps713xx has an on-chip supply voltage super- transient conditions will not cause reset to falsely visor (svs) that monitors the voltage at out2. the assert. reset output will assert if v out2 is below the reset the reset pin requires an external resistor to pull threshold (v it ). when out2 exceeds the reset the pin high during the unasserted state. a 10 k w to 1 threshold plus hysteresis (v hys ), the reset output m w resistor is suitable for most applications. if the will remain low for the specified delay time (t d ). when resistance is too low, the pin may not pull low enough out2 is disabled by en2 or the input voltage is to be recognized as a valid logic signal. if the pull-up below the under-voltage lockout (uvlo), the reset resistor is too large, the reset pin leakage may cause signal is automatically asserted. the functionality of the device not to pull high enough in the unasserted the reset circuit is shown in figure 26 and table 2 . state. the pull-up voltage for the reset pin should the output accuracy or output divider resistor toler- not exceed v in + 0.3 v; doing so will turn on internal ances have minimal effect on the relative v it esd protection devices and may damage the device. threshold accuracy. the reset threshold v it will scale accordingly to the actual output voltage. the reset figure 26. reset timing diagram table 2. reset pin truth table uvlo reset en2 asserted v out2 asserted x (1) yes x yes low x x yes high no v out2 > v it no high no v out2 < v it yes (1) x = don't care. 11 www .ti.com v o u t 1 v i t + v h y s v i t v i n 0 . 6 v 0 . 0 v v o u t 2 e n 1 e n 2 r e s e t t d t d t d = r e s e t d e l a y = u n d e f i n e d s t a t e
transient response shutdown power dissipation internal current limit thermal protection (4) tps71319 tps71334 sbvs055a ? december 2004 ? revised january 2005 depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection as with any regulator, increasing the size of the circuit may cycle on and off. this limits the dissipation output capacitor will reduce over/undershoot magni- of the regulator, protecting it from damage due to tude but increase duration of the transient response. overheating. in the adjustable version, the addition of a capacitor, c fb , from the output to the feedback pin will also any tendency to activate the thermal protection circuit improve stability and transient response. the transi- indicates excessive power dissipation or an inad- ent response of the tps713xx is enhanced with an equate heatsink. for reliable operation, junction tem- active pull-down that engages when the output is perature should be limited to +125 c maximum. to over-voltaged. the active pull-down decreases the estimate the margin of safety in a complete design output recovery time when the load is removed. (including heatsink), increase the ambient tempera- figure 14 in the typical characteristics section shows ture until the thermal protection is triggered; use the output transient response. worst-case loads and signal conditions. for good reliability, thermal protection should trigger at least +35 c above the maximum expected ambient con- dition of your application. this produces a worst-case both enable pins are active high and are compatible junction temperature of +125 c at the highest ex- with standard ttl-cmos levels. the device is only pected ambient temperature and worst-case load. completely disabled when both en1 and en2 are the internal protection circuitry of the tps713xx was logic low. in this state, the ldo is completely off and designed to protect against overload conditions. it the ground pin current drops to approximately was not intended to replace proper heatsinking. 100 na. with one output disabled, the ground pin continuously running the tps713xx into thermal current is slightly greater than half the nominal value. shutdown will degrade device reliability. when shutdown capability is not required, the enable pins should be connected to the input supply. the ability to remove heat from the die is different for each package type, presenting different consider- the tps713xx internal current limit helps protect the ations in the pcb layout. the pcb area around the regulator during fault conditions. during current limit, device that is free of other components moves the the output will source a fixed amount of current that is heat from the device to the ambient air. performance largely independent of the output voltage. data for a jedec high-k board is shown in the the tps713xx pmos-pass transistors have a built-in dissipation ratings table. using heavier copper will back diode that conducts reverse current when the increase the effectiveness in removing heat from the input voltage drops below the output voltage (that is, device. the addition of plated through-holes to during power-down). current is conducted from the heat-dissipating layers will also improve the heat-sink output to the input and is not internally limited. if effectiveness. extended reverse voltage operation is anticipated, power dissipation depends on input voltage and load external limiting may be appropriate. conditions. power dissipation is equal to the product of the output current times the voltage drop across the output pass element (v in to v out ): thermal protection disables both outputs when the junction temperature of either channel rises to ap- proximately +160 c, allowing the device to cool. power dissipation can be minimized by using the when the junction temperature cools to approxi- lowest possible input voltage necessary to assure the mately +140 c, the output circuitry is again enabled. required output voltage. 12 www .ti.com p d ( v i n v o u t ) i o u t
package option addendum www.ti.com 30-sep-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps71319drcr active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 arp tps71319drcrg4 active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 arp tps71319drct active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 arp tps71319drctg4 active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 arp tps71334drcr active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 aro tps71334drct active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 aro tps71334drctg4 active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 aro (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
package option addendum www.ti.com 30-sep-2014 addendum-page 2 (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps71319drcr vson drc 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 tps71319drct vson drc 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 tps71334drcr vson drc 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 tps71334drct vson drc 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 package materials information www.ti.com 1-oct-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps71319drcr vson drc 10 3000 367.0 367.0 35.0 tps71319drct vson drc 10 250 210.0 185.0 35.0 tps71334drcr vson drc 10 3000 367.0 367.0 35.0 tps71334drct vson drc 10 250 210.0 185.0 35.0 package materials information www.ti.com 1-oct-2014 pack materials-page 2

www.ti.com
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2016, texas instruments incorporated

▲Up To Search▲

Price & Availability of TPS71319-16

	To Download TPS71319-16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .